Datasheet

89
32117D–AVR-01/12
AT32UC3C
8.5.10 System RC Oscillator (RCSYS)
The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in
the STATIC sleep mode. The system RC oscillator operates at a nominal frequency of 115 kHz,
and is calibrated using the RCCR.CALIB Calibration field. After a Power On Reset, the
RCCR.CALIB field is loaded with a factory defined value stored in the Flash fuses.
Although it is not recommended, it is still possible to override the default factory settings by writ-
ing to the RCCR.CALIB field. To prevent unexpected writes due to software bugs, write access
to this register is protected by a locking mechanism, for details please refer to the UNLOCK reg-
ister description.
8.5.11 8MHz / 1MHz RC Oscillator (RC8M)
The 8MHz / 1MHz RC oscillator (RC8M) operates at a nominal frequency of 8MHz or 1 MHz
according to RCCR8.FREQMODE bit. It is calibrated using the RCCR8.CALIB Calibration field.
After a Power On Reset, the RCCR8.CALIB field is automatically loaded with the RC8M_CALIB
field of the Oscillator Calibration register
, a factory defined value stored in the factory page of the
Flash.
If the user wants to run the oscillator at 1MHz or if the device operates at VDDIN_5 within the 5V
range, it has to write the RCCR8.CALIB field with the corresponding field from the Oscillator Cal-
ibration register.
Although it is not recommended, it is still possible to override the default factory settings by writ-
ing to the RCCR8.CALIB field. To prevent unexpected writes due to software bugs, write access
to this register is protected by a locking mechanism, for details please refer to the UNLOCK reg-
ister description.
8.5.12 RC120M
The 120MHz RC Oscillator can be used for the main clock in the device, as described in the
Power Manager chapter. To enable the clock, the user must write a one to the EN bit in the
RC120MCR register, and read back the RC120MCR register until the EN bit reads one. The
clock is disabled by writing a zero to the EN bit.
The oscillator is automatically switched off in certain sleep modes to reduce power consumption,
as described in the Power Manager chapter.
8.5.13 General Purpose Low Power Registers (GPLP)
The GPLP registers are 32-bit registers that are reset only by power-on-reset. User software can
use these registers to save context variables in a very low power mode.
8.5.14 Interrupts
The SCIF has separate interrupt requests:
• AE - Access Error:
– Set when a protected SCIF register was accessed without first being correctly
unlocked.
• PLL1LOCKLOST - PLL1 lock lost:
– Set when a 0 to 1 transition on the PCLKSR.PLL1LOCKLOST bit is detected.
• PLL0LOCKLOST - PLL0 lock lost:
– Set when a 0 to 1 transition on the PCLKSR.PLL0LOCKLOST bit is detected.