Datasheet

878
32117D–AVR-01/12
AT32UC3C
Figure 32-6. Plug-in Detection Input Block Diagram
The control logic of the USB_VBUS pad outputs two signals:
• The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 1.4V.
• The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 4.4V.
In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.
• It is cleared when the voltage on the VBUS pad is lower than 1.4V.
In host mode, the USBSTA.VBUS bit follows a hysteresis based on Session_valid and
Va_Vbus_valid:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.
• It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V.
The VBUS Transition Interrupt (VBUSTI) bit in USBSTA is set on each transition of the USB-
STA.VBUS bit.
The USBSTA.VBUS bit is operational regardless of whether the USBC is enabled or not.
32.6.1.9 ID detection
Figure 32-7 shows how the ID transitions are detected.
Figure 32-7. ID Detection Input Block Diagram
VBUSTI
USB_VBUS
VBUS
USBSTA
GND
VDD
Pad Logic
Logic
Session_valid
Va_Vbus_valid
R
PU
R
PD
VBUS_pulsing
VBUS_discharge
R
PU
UIMOD
USBCON
USB_ID
ID
USBSTA
VDD
UIDE
USBCON
1
0
IDTI
USBSTA
I/O Controller