Datasheet

875
32117D–AVR-01/12
AT32UC3C
The USBC can be disabled at any time by writing a zero to USBCON.USBE, this acts as a hard-
ware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, and UIMOD bits in USBCON,
and the LS bits in UDCON are not reset.
32.6.1.2 Interrupts
One interrupt vector is assigned to the USBC.
See Section 32.6.2.18 and Section 32.6.3.16 for further details about device and host interrupts.
There are two kinds of general interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing general interrupts are:
• The ID Transition Interrupt (IDTI)
• The VBUS Transition Interrupt (VBUSTI)
• The SRP Interrupt (SRPI)
• The Role Exchange Interrupt (ROLEEXI)
The exception general interrupts are:
• The VBUS Error Interrupt (VBERRI)
• The B-Connection Error Interrupt (BCERRI)
• The HNP Error Interrupt (HNPERRI)
• The Suspend Time-Out Interrupt (STOI)
See Section 32.5.4 for asynchronous interrupts.
32.6.1.3 Frozen clock
When the USB clock is frozen, it is still possible to access the following bits: OTGPADE,
VBUSPO, UIDE, UIMOD, FRZCLK, and USBE in the USBCON register, and LS in the UDCON
register.
When FRZCLK is set, only the asynchronous interrupts can trigger a USB interrupt (see Section
32.5.4).
32.6.1.4 Speed control
• Device mode
When the USBC interface is in device mode, the speed selection is done by the UDCON.LS bit,
connecting an internal pull-up resistor to either DP (full-speed mode) or DM (low-speed mode).
The LS bit shall be written before attaching the device, which can be simulated by clearing the
UDCON.DETACH bit.