Datasheet

874
32117D–AVR-01/12
AT32UC3C
32.6 Functional Description
32.6.1 USB General Operation
32.6.1.1 Initialization
After a hardware reset, the USBC is disabled. When enabled, the USBC runs in either device
mode or in host mode according to the ID detection.
If the USB_ID pin is not connected to ground and the pull-up is enabled, the USB_ID state bit in
the General Status register (USBSTA.ID) will be set and the device mode will be enabled.
If a low level is detected on the USB_ID pin, the USBSTA.ID bit will be cleared and the host
mode will be enabled.
Figure 32-2. General states
After a hardware reset, the USBC is in the Reset state. In this state:
• The module is disabled. The USBC Enable bit in the General Control register
(USBCON.USBE) is reset.
• The module clock is stopped in order to minimize power consumption. The Freeze USB Clock
bit in USBCON (USBCON.FRZCLK) is set.
• The USB pad is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The USBSTA.ID bit and the VBUS Level bit (USBSTA.VBUS) reflect the states of the USB_ID
and USB_VBUS input pins.
• The VBUS Level bit (USBSTA.VBUS) reflects the states of the USB_VBUS input pins.
• The OTG Pad Enable (OTGPADE), VBUS Polarity (VBUSPO), Freeze USB Clock (FRZCLK),
USBC Enable (USBE), USB_ID Pin Enable (UIDE), USBC Mode (UIMOD) in USBCON, and
the Low-Speed mode bit in the Device General Control register (UDCON.LS) can be written
to by software, so that the user can configure pads and speed before enabling the module.
These values are only taken into account once the module has been enabled and unfrozen.
After writing a one to USBCON.USBE, the USBC enters device or host mode (according to the
ID detection) in idle state.
Refer to Section 32.6.2 for the basic operation of the device mode.
Refer to Section 32.6.3 for the basic operation of the host mode.
Device
Reset
USBE = 0
<any
other
state>
USBE = 1
ID = 1
Macro off:
USBE = 0
Clock stopped:
FRZCLK = 1
USBE = 0
Host
USBE = 0
HW
RESET
USBE = 1
ID = 0