Datasheet

873
32117D–AVR-01/12
AT32UC3C
32.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
32.5.1 I/O Lines
The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign the desired USBC pins to their peripheral functions.
If the USB_ID pin is used the user must also enable its internal pull-up resistor.
32.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the USBC, the USBC will stop func-
tioning and resume operation after the system wakes up from sleep mode.
32.5.3 Clocks
The USBC has two bus clocks connected: One High Speed Bus clock (CLK_USBC_HSB) and
one Peripheral Bus clock (CLK_USBC_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled by the Power Manager. It is
recommended to disable the USBC before disabling the clocks, to avoid freezing the USBC in
an undefined state.
The 48MHz USB clock is generated by a dedicated generic clock from the SCIF module. Before
using the USB, the user must ensure that the USB generic clock (GCLK_USBC) is enabled at
48MHz in the SCIF module.
32.5.4 Interrupts
The USBC interrupt request line is connected to the interrupt controller. Using the USBC inter-
rupt requires the interrupt controller to be programmed first.
The USBC asynchronous interrupts can wake the CPU from any sleep mode:
• The ID Transition Interrupt (IDTI)
• The VBUS Transition Interrupt (VBUSTI) if the bandgap voltage reference is ON (Refer to the
Power Manager chapter)
• The Wakeup Interrupt (WAKEUP)
• The Host Wakeup Interrupt (HWUPI)