Datasheet

86
32117D–AVR-01/12
AT32UC3C
Figure 8-3. Generic clock generation
8.5.4.1 Enabling a generic clock
A generic clock is enabled by writing a one to the CEN bit in GCCTRL to one. Each generic clock
can individually select a clock source by setting the OSCSEL bits. The source clock can option-
ally be divided by writing a one to DIVEN and the division factor to DIV, resulting in the output
frequency:
f
GCLK
= f
SRC
/ (2*(DIV+1))
8.5.4.2 Disabling a generic clock
The generic clock can be disabled by writing a zero to CEN or entering a sleep mode that dis-
ables the PB clocks. In either case, the generic clock will be switched off on the first falling edge
after the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still
read as one until the next falling edge occurs, and the clock is actually switched off. When writ-
ing a zero to CEN, the other bits in GCCTRL should not be changed until CEN reads as zero, to
avoid glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
8.5.4.3 Changing clock frequency
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
8.5.4.4 Generic clock implementation
In AT32UC3C, the generic clocks are allocated to different functions as shown in Table 8-2.
Divider
OSCSEL
Generic Clock
DIV
0
1
DIVEN
Mask
CEN
Sleep Controller
Table 8-2. Generic clock allocation
Clock number Function Name
0 USB clock (48 MHz) GCLK_USBC
1 CANIF GCLK_CANIF
2 AST GCLK_AST