Datasheet

85
32117D–AVR-01/12
AT32UC3C
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus becoming unstable.
Figure 8-2. PLL with control logic and filters
8.5.3.1 Enabling the PLL
PLLn is enabled by writing a one to the PLLEN bit in the PLLn register. PLLOSC selects Oscilla-
tor 0 or 1 as clock source. The PLLMUL and PLLDIV bit fields must be written with the
multiplication and division factors.
The PLLn.PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
8.5.4 Generic Clocks
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF contains an implementation defined
number of generic clocks that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either clock source listed in ”Generic Clock Source” on
page 119. The selected source can optionally be divided by any even integer up to 512. Each
clock can be independently enabled and disabled, and is also automatically disabled along with
peripheral clocks by the Sleep Controller in the Power Manager.
PLL
Output
Divider
0
1
Osc0 clock
Osc1 clock
PLLOSC
PLLEN
PLLOPT
PLLMUL
LOCK
Mask
PLL clock
Input
Divider
f
IN
PLLDIV