Datasheet

815
32117D–AVR-01/12
AT32UC3C
30.8.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK,
and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to dis-
able the IISC before writing a new value into MR.
• IWS24: IWS TDM Slot Width
0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit
1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit
Refer to Table 30-2, “Slot Length,” on page 808.
• IMCKMODE: Master Clock Mode
0: No Master Clock generated (generic clock is used as ISCK output)
1: Master Clock generated (generic clock is used as IMCK output)
Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to Section 30.6.6 ”Serial
Clock and Word Select Generation” on page 807 and Table 30-2, “Slot Length,” on page 808.
• IMCKFS: Master Clock to fs Ratio
Master Clock frequency is 8*(NBCHAN+1)*(IMCKFS+1) times the sample rate, i.e. IWS frequency:
31 30 29 28 27 26 25 24
IWS24 IMCKMODE IMCKFS
23 22 21 20 19 18 17 16
TDMFS - - - NBCHAN
15 14 13 12 11 10 9 8
- TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO
76543210
FO RM AT - DATA LE NGT H - M ODE
Table 30-4. Master Clock to Sampling Frequency (fs) Ratio
fs Ratio
IMCKFS
2 channels 4 channels 6 channels 8 channels
16 fs 0 - - -
32 fs 1 0 - -
48fs2-0-
64 fs 3 1 - 0
96fs 5 2 1 -
128 fs 7 3 - 1
192fs 11 5 3 2