Datasheet

772
32117D–AVR-01/12
AT32UC3C
ID received: 000.0010.1001 b 000.0010.1001 b
IDT: 000.0010.1010 b 000.0100.1000 b
IDM: 111.1111.0000 b 111.1111.0000 b
Comparison: 111.1111.- - - - b 111.1001.- - - - b
Accepted: Y N
The filtering process scans each MOb enabled and configured for reception, from MOb 0, in
order to find the MOb that matches the conditions. The first MOb to match is selected for storing
the message once received successfully. If no MOb matches, the message is discarded.
29.6.5 Channel Interrupts
There are several sources of interrupts and user can mask each of them. Some sources are
grouped into a single interrupt request line. There are 5 interrupt request lines per channel.
• Wake-up interrupt: Wake-up condition detected
• Error interrupt: Any CAN error detected during a communication
• Bus off interrupt: The CAN protocol engine entered in bus off state
• Took interrupt: At least one MOb completed a transmission
• Waxed interrupt: At least one MOb completed a reception
The CANIMR and MOBIMR are used for masking interrupts. These registers are read-only. In
order to set or clear interrupt mask bits, user must write to the following registers:
• CANIER / MOBIER: Writing a bit to one sets the corresponding bit in CANIMR / MOBIMR.
Writing a bit to 0 has no effect.
• CANIDR / MOBIDR: Writing a bit to one clears the corresponding bit in CANIMR / MOBIMR.
Writing a bit to 0 has no effect.
To acknowledge an interrupt request, user must clear the corresponding bit in the corresponding
status register (CANISR, MTXISR or MRXISR). To clear status bits, user must access the fol-
lowing write-only registers:
• CANISCR / MTXISCR / MRXISCR: Writing a bit to one clears the corresponding bit in
CANISR / MTXISR / MRXISR. Writing a bit to 0 has no effect.
For each MOb, the bits TXOK and RXOK are also accessible in MOBSCR register for clear
access and MOBSR register for read access.