Datasheet

770
32117D–AVR-01/12
AT32UC3C
Figure 29-9. Identifier Mask (IDM)
Figure 29-10. Data Fields (64 bits)
29.6.3.2 Transmission
Once a message has been written into RAM at the address corresponding to the selected MOb,
user controls transmission through the MOBCTRL register:
• DLC[3:0] field: Data length code i.e. the number of byte to send, from 0 to 8
• DIR bit: MOb direction, 1 stands for transmission
Once MOb is enabled (by writing to MOBER), transmission starts as soon as bus idle is detected
on the CAN bus. User can check if channel is sending a frame by reading CANSR.TS bit.
At the end of the successful transmission bit MOBESR.MENn is cleared and MOBSR.TXOK is
set. To acknowledge interrupt and to free the MOb user must clear this status bit by writing a one
to the associated bit in MOb Status Clear Register (MOBSCR).
CAN errors detected during transmission are reported in CANISR. Message will not be transmit-
ted but the MOb remains enabled. The message will be automatically re-transmitted until
successfully transmitted.
Several MObs can be enabled/disabled in one operation by writing to the MOBER/MOBDR
registers:
• MOBER: Each bit correspond to an enable bit for a single MOb. Write 1 to set a bit and 0 to
keep it unchanged.
• MOBDR: Each bit correspond to an enable bit for a single MOb. Write 1 to clear a bit and 0 to
keep it unchanged.
If several MObs are enabled, the MOb with the lowest number is transmitted first. This rule is
also used in case of a re-transmission (due to transmission error or contention).
29.6.3.3 Reception
Once the expected message has been written into RAM at the address corresponding to the
selected MOb, user controls reception through the MOBCTRL register:
• DLC[3:0] field: Data length code i.e. the number of byte to receive, from 0 to 8
- IDM (29 bits)
293031 28 0
- -
293031 28 0
IDM (11 bits)
1011
Standard format
Extended format
RTRM IDEM
RTRM IDEM
DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4
31 23 15 7 081624
@
@+4