Datasheet

764
32117D–AVR-01/12
AT32UC3C
29.5.5 Interrupts
CANIF interrupt request line is connected to the interrupt controller. Using the CANIF interrupt
requires the interrupt controller to be programmed first.
29.5.6 Debug Operation
All CAN channels are disabled when the CPU enters Debug mode. Communication in progress
is not stopped. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Refer-
ence Manual, and the OCD Module Configuration section, for details.
29.6 Functional Description
29.6.1 Channel Configuration
Channel configuration is done via the Configuration Register (CANCFG). This register is not
write accessible once the channels have been enabled.
29.6.1.1 Bit timing
This section refers to chapter 8 (Bit timing requirements) of the CAN Specification.
The CAN bit rate is defined by the nominal bit time. Nominal bit time is divided into 4 time
segments.
Figure 29-2. Partition of the Bit Time
The duration of each time segment is divided into time quanta (TQ). The total number of TQ in a
bit time must be in the range [8..25].
The Time Quantum is a fixed unit of time derived from the GCLK_CANIF clock period:
TQ = Prescaler x
PGCLK_CANIF = (CANCFG.PRES+1) x PGCLK_CANIF
Re-synchronization may lengthen or shorten the bit time, the upper bound is given by Synchroni-
zation Jump Width field in the Configuration Register (CANCFG.SJW).
The value of all previous parameters are defined in CANCFG register.
Table 29-2. CAN Parameter Settings
Parameter Range CANCFG field
SYNC_SEG 1 -
PROP_SEG [1..8]TQ PRS + 1
PHASE_SEG1 [1..8]TQ PHS1 + 1
SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
Nominal bit time
Sample Point