Datasheet

763
32117D–AVR-01/12
AT32UC3C
29.3 Block Diagram
Figure 29-1. CANIF Block Diagram
29.4 I/O Lines Description
29.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
29.5.1 I/O Lines
CANIF pins are multiplexed with other peripherals. User must first program the I/O Controller to
give control of the pins to the CANIF.
29.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by CANIF, it will stop functioning and
resume operation after the system wakes up from sleep mode.
29.5.3 Clocks
CANIF is connected to both the HSB and the PB, and therefore uses a HSB clock
(CLK_CANIF_HSB) and a PB clock (CLK_CANIF_PB). These clocks are generated by the
Power Manager. These clocks are enabled at reset, and can be disabled in the Power Manager.
CANIF uses a GCLK as clock source (CAN clock) for the CAN bus communication
(GCLK_CANIF). User must make sure this clock is running and frequency is correct before any
operation.
29.5.4 Memory
Messages can be stored in CPU or HSB RAM, so user must allocate RAM space for CAN
messages.
RAM
HSB
TXLINE(0)
RXLINE(0)
.
.
.
PB
Msg Handling
& Filtering
Protocol
Engine
CANIF
CAN
clock
TXLINE(n)
RXLINE(n)
Table 29-1. I/O Lines Description
Pin Name Pin Description Type
TXLINE(n) Transmission line of channel n Output
RXLINE(n) Reception line of channel n Input