Datasheet

761
32117D–AVR-01/12
AT32UC3C
28.10 Module Configuration
The specific configuration for each TWIS instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 28-7. Module Configuration
Feature TWIM0 TWIM1 TWIM2
SMBus ALERT interface Implemented Implemented Not Implemented
Table 28-8. Module Clock Name
Module Name Clock Name Description
TWIS0 CLK_TWIS0 Peripheral Bus clock from the PBA clock domain
TWIS1 CLK_TWIS1 Peripheral Bus clock from the PBA clock domain
TWIS2 CLK_TWIS2 Peripheral Bus clock from the PBC clock domain
Table 28-9. Register Reset Values
Register Reset Value
VR 0x00000120
PR 0x00000000