Datasheet

731
32117D–AVR-01/12
AT32UC3C
27.10 Module Configuration
The specific configuration for each TWIM instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 27-7. Module Configuration
Feature TWIM0 TWIM1 TWIM2
SMBus ALERT interface Implemented Implemented Not Implemented
Table 27-8. Module Clock Name
Module Name Clock Name Description
TWIM0 CLK_TWIM0 Peripheral Bus clock from the PBA clock domain
TWIM1 CLK_TWIM1 Peripheral Bus clock from the PBA clock domain
TWIM2 CLK_TWIM2 Peripheral Bus clock from the PBC clock domain
Table 27-9. Register Reset Values
Register Reset Value
VR 0x0000 0101
PR 0x0000 0000