Datasheet

32117D–AVR-01/12

AT32UC3C

7.7.6 Divided Clock Mask

Name: PBADIVMASK/PBBDIVMASK/PBCDIVMASK

Access Type: Read/Write

Offset: 0x0040, 0x0044, 0x0048

Reset Value: -

•

MASK: Clock Mask

If bit n is written to zero, the clock divided by 2

(n+1)

is stopped. If bit n is written to one, the clock divided by 2

(n+1)

is enabled

according to the current power mode. Table 7-8 and Table 7-9 show what clocks are affected by the different MASK bits.

31 30 29 28 27 26 25 24

--------

23 22 21 20 19 18 17 16

- ------

15 14 13 12 11 10 9 8

--------

76543210

- MASK[6:0]

Table 7-8. PBA Divided Clock Mask

Bit USART0 USART2 USART3 TC1

0 - TIMER1_CLOCK2

1- -

2 CLK_PBA_USART_DIV TIMER1_CLOCK3

3- -

4 - TIMER1_CLOCK4

5- -

6 - TIMER1_CLOCK5

Table 7-9. PBC Divided Clock Mask

Bit USART1 USART4 TC0

0 - TIMER0_CLOCK2

1- -

2 CLK_PBC_USART_DIV TIMER0_CLOCK3

3- -