Datasheet

32117D–AVR-01/12

AT32UC3C

7.7.5 Clock Mask

Name: CPU/HSB/PBA/PBBMASK

Access Type: Read/Write

Offset: 0x0020, 0x0024, 0x0028, 0x002C, 0x0030

Reset Value: -

•

MASK: Clock Mask

• If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current

power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit,

is shown in Table 7-7.

31 30 29 28 27 26 25 24

MASK[31:24]

23 22 21 20 19 18 17 16

MASK[23:16]

15 14 13 12 11 10 9 8

MASK[15:8]

76543210

MASK[7:0]

Table 7-7. Maskable module clocks in AT32UC3C.

Bit CPUMASK HSBMASK PBAMASK PBBMASK PBCMASK

0 - SAU INTC FLASHC PDCA

1 OCD PDCA PM USBC MDMA

2 - MDMA SCIF HMATRIX USART1

3 - USBC AST SAU SPI0

4 - CANIF WDT SMC CANIF

5 - HFLASHC EIC SDRAMC TC0

6 - PBA Bridge FREQM MACB ADCIFA

7 - PBB Bridge GPIO - USART4

8 - PBC Bridge USART0 - TWIM2

9 - HSB RAM USART2 - TWIS2

10 - EBI USART3 - -

11 - MACB SPI1 - -

12 - PEVC TWIM0 - -