Datasheet

32117D–AVR-01/12

AT32UC3C

• PAR: Parity Type

• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase

If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):

SYNC = 0: USART operates in Asynchronous Mode.

SYNC = 1: USART operates in Synchronous Mode.

If USART operates in SPI Mode (MODE = 0xE or 0xF):

CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with

CPOL to produce the required clock/data relationship between master and slave devices.

• CHRL: Character Length.

• USCLKS: Clock Selection

Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the

end of this chapter.

Table 25-19.

PAR Parity Type

0 0 0 Even parity

001Odd parity

0 1 0 Parity forced to 0 (Space)

0 1 1 Parity forced to 1 (Mark)

1 0 x No parity

1 1 x Multidrop mode

Table 25-20.

CHRL Character Length

0 0 5 bits

0 1 6 bits

1 0 7 bits

1 1 8 bits

Table 25-21.

USCLKS Selected Clock

0 0 CLK_USART

0 1 CLK_USART/DIV

(1)

10Reserved

CLK