Datasheet

619
32117D–AVR-01/12
AT32UC3C
Figure 25-52. Master Node with Peripheral DMA Controller (PDCM=0)
25.6.12.2 Slave Node Configuration
In this configuration, the Peripheral DMA Controller transfers only the DATA. The Identifier must
be read by the user in the LIN Identifier register (LINIR). The LIN mode must be written by the
user in the LIN Mode register (LINMR).
The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH).
The READ buffer contains the DATA if the USART receives the response
(NACT=SUBSCRIBE).
IMPORTANT: if the NACT configuration for a frame is PUBLISH, the US_LINMR register, must
be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set
the TXREADY flag and the corresponding Peripheral DMA Controller write transfer request.
Figure 25-53. Slave Node with Peripheral DMA Controller
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RXRDY
TXRDY
Peripheral
bus
USART LIN
CONTROLLER
DATA 0
DATA N
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READ BUFFER
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
Peripheral DMA
Controller
RXRDY
Peripheral
bus
DATA 0
DATA 1
DATA N
WRITE BUFFER
Peripheral DMA
Controller
USART LIN
CONTROLLER
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DATA 0
DATA N
RXRDY
Per ipheral
Bus
READ BUFFER
NACT = SUBSCRIBE
DATA 0
DATA N
TXRDY
Peripheral
bus
WRITE BUFFER
USART LIN
CONTROLLER
USART LIN
CONTROLLER
Peripheral DMA
Controller
Peripheral DMA
Controller