Datasheet

618
32117D–AVR-01/12
AT32UC3C
25.6.12 LIN Frame Handling With The Peripheral DMA Controller
The USART can be used in association with the Peripheral DMA Controller in order to transfer
data directly into/from the on- and off-chip memories without any processor intervention.
The Peripheral DMA Controller uses the trigger flags, TXRDY and RXRDY, to write or read into
the USART. The Peripheral DMA Controller always writes in the Transmit Holding register (THR)
and it always reads in the Receive Holding register (RHR). The size of the data written or read by
the Peripheral DMA Controller in the USART is always a byte.
25.6.12.1 Master Node Configuration
The user can choose between two Peripheral DMA Controller modes by the PDCM bit in the LIN
Mode register (LINMR):
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the
Peripheral DMA Controller in the Transmit Holding register THR (instead of the LIN Mode
register LINMR). Because the Peripheral DMA Controller transfer size is limited to a byte, the
transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS,
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is
written.
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
the user in the LIN Mode register (LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
Figure 25-51. Master Node with Peripheral DMA Controller (PDCM=1)
|
|
|
|
|
|
|
|
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
Peripheral
bus
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
READ BUFFER
NODE ACTION = PUBLISH
NODE ACTION = SUBSCRIBE
Peripheral DMA
Controller
Peripheral DMA
Controller
USART LIN
CONTROLLER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
USART LIN
CONTROLLER
TXRDY
Peripheral
bus