Datasheet

606
32117D–AVR-01/12
AT32UC3C
The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section
25.6.1).
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8
Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the
new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) gives the
new fractional part (LINFP).
Once the Synch Field has been entirely received, the clock divider (LINCD) and the fractional
part (LINFP) are updated in the LIN Baud Rate register (LINBRR) with the computed values, if
the synchronization is not disabled by the bit SYNCDIS in the LIN Mode register (LINMR).
If after reception of the Synch Field, it appears that the computed baudrate deviation compared
to the initial baud rate is superior to the maximum tolerance FToI_Unsynch (+/- 15%) then the
clock divider (LINCD) and the fractional part (LINFP) are not updated and the error bit STE in the
Channel Status register CSR is set to 1.
If after reception of the Synch Field, it appears that the sampled Synch character is not equal to
0x55 then the clock divider (LINCD) and the fractional part (LINFP) are not updated, and the
error bit ISFE in the Channel Status register (CSR) is set to 1.
The bits LINSTE and LINISFE are reset by writing the bit RSTSTA at 1 in the Control register
(CR).
Figure 25-42. Slave Node Synchronization
The accuracy of the synchronization depends on several parameters:
• The nominal clock frequency (F
Nom
) (the theoretical slave node clock frequency)
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
The following formula is used to compute the deviation of the slave bit rate relative to the master
bit rate after synchronization (F
SLAVE
is the real slave node clock frequency).
RXD
Baud Rate
Clock
LINIDRX
Synchro Counter 000_0011_0001_0110_1101
BRGR
Clcok Divider (CD)
0000_0110_0010_1101
BRGR
Fractional Part (FP)
101
Initial CD
Initial FP
Reset
Start
Bit
10101010
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
Baudrate_deviation 100
α[ 82Over–()β+ ] Baudrate×××
8F
SLAVE
×
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×
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