Datasheet
605
32117D–AVR-01/12
AT32UC3C
25.6.9.7 Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At
any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break
Field. As long as a Break Field has not been detected, the USART stays idle and the received
data are not taken in account.
When a Break Field has been detected, the USART expects the Synch Field character to be
0x55. This field is used to update the actual baud rate in order to stay synchronized (see Section
25.6.9.8). If the received Synch character is not 0x55, an Inconsistent Synch Field error is gen-
erated (see Section 25.6.10).
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier has been received, the flag LINID is set to “1”. At this moment the field
IDCHR in the LIN Identifier register (LINIR) is updated with the received character. The Identifier
parity bits can be automatically computed and checked (see Section 25.6.9.9).
If the header is not entirely received within the time given by the maximum length of the header
THeader_Maximum, the error bit LINHTE in the Channel Status register (CSR) is set to 1.
The bits LINID, LINBK and LINHTE are reset by writing the bit RSTSTA to 1 in the Control regis-
ter (CR).
Figure 25-40. Header Reception
25.6.9.8 Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
Figure 25-41. Synch Field
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit
10101010
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID4ID3 ID6ID5 ID7
Stop
Bit
Synch Byte = 0x55
Baud Rate
Clock
RXD
Write US_CR
With RSTSTA=1
US_LINIR
LINID
Start
bit
Stop
bit
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit 2 Tbit