Datasheet

600
32117D–AVR-01/12
AT32UC3C
Figure 25-37. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 25-38. SPI Transfer Format (CPHA=0, 8 bits per transfer)
CLK cycle (for reference)
CLK
(CPOL= 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
MSB
1
CLK
(CPOL= 0)
3
5
6
78
LSB
1234
6
65
5
43
21
LSB
24
CLK cycle (for reference)
CLK
(CPOL= 0)
CLK
(CPOL= 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB 6 5
MSB 6 5
4
43
32
21
1
LSB
LSB
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