Datasheet

598
32117D–AVR-01/12
AT32UC3C
25.6.8.2 Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode: See Section “25.6.1.4” on page 570. However, there are some restrictions:
In SPI Master Mode:
• the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set
to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK
pin.
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of
must be superior or equal to 4.
• if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must
be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the
internal clock is selected (CLK_USART).
In SPI Slave Mode:
• the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the
Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is
provided directly by the signal on the USART CLK pin.
• to obtain correct behavior of the receiver and the transmitter, the external clock (CLK)
frequency must be at least 4 times lower than the system clock.