Datasheet

59
32117D–AVR-01/12
AT32UC3C
7.7 User Interface
Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end
of this chapter.
Table 7-5. PM Register Memory Map
Offset Register Name Access Reset State
0x0000 Main Clock Control MCCTRL Read/Write 0x00000000
0x0004 CPU Clock Select CPUSEL Read/Write 0x00000000
0x0008 HSB Clock Select HSBSEL Read Only 0x00000000
0x000C PBA Clock Select PBASEL Read/Write 0x00000000
0x00010 PBB Clock Select PBBSEL Read/Write 0x00000000
0x0014 PBC Clock Select PBCSEL Read/Write 0x00000000
0x0020 CPU Mask CPUMASK Read/Write 0x00000003
0x0024 HSB Mask HSBMASK Read/Write 0x00003FFF
0x0028 PBA Mask PBAMASK Read/Write 0x07FFFFFF
0x002C PBB Mask PBBMASK Read/Write 0x0000007F
0x0030 PBC Mask PBCMASK Read/Write 0x000003FF
0x0040 PBA Divided Mask PBADIVMASK Read/Write 0x0000007F
0x0044 PBB Divided Mask PBBDIVMASK Read/Write 0x0000007F
0x0048 PBC Divided Mask PBCDIVMASK Read/Write 0x0000007F
0x0054 Clock Failure Detector Control CFDCTRL Read/Write 0x00000000
0x0058 Unlock Register UNLOCK Write Only -
0x00C0 PM Interrupt Enable Register IER Write Only 0x00000000
0x00C4 PM Interrupt Disable Register IDR Write Only 0x00000000
0x00C8 PM Interrupt Mask Register IMR Read Only 0x00000000
0x00CC PM Interrupt Status Register ISR Read Only 0x00000000
0x00D0 PM Interrupt Clear Register ICR Write Only 0x00000000
0x00D4 Status Register SR Read Only 0x00000020
0x0180 Reset Cause Register RCAUSE Read Only Latest Reset Source
0x0184 Wake Cause Register WCAUSE Read Only Latest Wake Source
0x0188 Asynchronous Wake Enable AWEN Read/Write 0x00000000
0x03F8 Configuration Register CONFIG Read Only -
(1)
0x03FC Version Register VERSION Read Only -
(1)