Datasheet

585
32117D–AVR-01/12
AT32UC3C
Figure 25-22. Timeguard Operations
Table 25-8 indicates the maximum length of a timeguard period that the transmitter can handle
in relation to the function of the Baud Rate.
25.6.3.11 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of
frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the
Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at
0. Otherwise, the receiver loads a counter with the value programmed in TO. This counter is
decremented at each bit period and reloaded each time a new character is received. If the coun-
ter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on
RXD before a new character is received will not provide a time-out. This prevents having to
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
B
aud Rate
Clock
Start
Bit
TG = 4
Write
THR
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Stop
Bit
TXRDY
T
XEMPTY
TG = 4
Table 25-8. Maximum Timeguard Length Depending on Baud Rate
Baud Rate Bit time Timeguard
Bit/sec µs ms
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
33400 29.9 7.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21