Datasheet

581
32117D–AVR-01/12
AT32UC3C
Figure 25-18. FSK Modulator Output
25.6.3.6 Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 25-19 illustrates a character reception in synchronous mode.
Figure 25-19. Synchronous Mode Character Reception
25.6.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register
(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while
the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into
RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register
(CR) with the RSTSTA (Reset Status) bit at 1.
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
NRZ stream
10 0 1
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit
Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock