Datasheet

570
32117D–AVR-01/12
AT32UC3C
25.6.1.3 Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
The modified architecture is presented below:
Figure 25-3. Fractional Baud Rate Generator
25.6.1.4 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in BRGR.
Error 1
ExpectedBaudRate
ActualBaudRate
-------------------------------------------------- -
⎝⎠
⎛⎞
–=
Baudrate
SelectedClock
82 Over–()CD
FP
8
-------+
⎝⎠
⎛⎞
⎝⎠
⎛⎞
---------------------------------------------------------------- -=
USCLKS
CD
Modulus
Control
FP
FP
CD
glitch-free
logic
16-bit Counter
OVER
FIDI
SYNC
Sampling
Divider
CLK_USART
CLK_USART/DIV
Reserved
CLK
CLK
BaudRate
Clock
Sampling
Clock
SYNC
USCLKS = 3
>1
1
2
3
0
0
1
0
1
1
0
0
BaudRate
SelectedClock
CD
--------------------------------------=