Datasheet

32117D–AVR-01/12

AT32UC3C

7.6.5.1 Power-on Reset Detector

The Power-on Reset 1.8V (POR18) detector monitors the VDDCORE supply pin and generates

a Power-on Reset (POR) when the device is powered on. The POR is active until the

VDDCORE voltage is above the power-on threshold level (V

POT

). The POR will be re-generated

if the voltage drops below the power-on threshold level. See Electrical Characteristics for para-

metric details.

7.6.5.2 External Reset

The external reset detector monitors the RESET_N pin state. By default, a low level on this pin

will generate a reset.

7.6.6 Clock Failure Detector

This mechanism automatically switches the main clock source to the safe RCSYS clock when

the main clock source fails. This may happen when an external crystal is selected as a source

for the main clock and the crystal is not mounted on the board. The main clock is compared with

RCSYS, and if no rising edge of the main clock is detected during one RCSYS period, the clock

is considered to have failed.

The detector is enabled by writing a one to the Clock Failure Detection Enable bit in the Clock

Failure Detector Control Register (CFDCTRL.CFDEN). As soon as the detector is enabled, the

clock failure detector will monitor the divided main clock. Note that the detector does not monitor

the main clock if RCSYS is the source of the main clock, or if the main clock is temporarily not

available (startup-time after a wake-up, switching timing etc.), or in sleep mode where the main

clock is driven by the RCSYS (Stop and DeepStop mode). When a clock failure is detected, the

main clock automatically switches to the RCSYS clock and the Clock Failure Detected (CFD)

interrupt is generated if enabled. The MCCTRL register is also changed by hardware to indicate

that the main clock comes from RCSYS.

7.6.7 Interrupts

The PM has a number of interrupt sources:

• AE - Access Error,

– A lock protected register is written to without first being unlocked.

• CKRDY - Clock Ready:

– New Clock Select settings in the CPUSEL/PBxSEL registers have taken effect. (A

zero-to-one transition on SR.CKRDY is detected).

• CFD - Clock Failure Detected:

– The system detects that the main clock is not running.

The Interrupt Status Register contains one bit for each interrupt source. A bit in this register is

set on a zero-to-one transition of the corresponding bit in the Status Register (SR), and cleared

by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). The interrupt

sources will generate an interrupt request if the corresponding bit in the Interrupt Mask Register

is set. The interrupt sources are ORed together to form one interrupt request. The Power Man-

ager will generate an interrupt request if at least one of the bits in the Interrupt Mask Register

(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable

Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear