Datasheet

568
32117D–AVR-01/12
AT32UC3C
– Full LIN error checking and reporting
– Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
– Generation of the Wakeup signal
• Test modes
– Remote loopback, local loopback, automatic echo
25.6.1 Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (MR) between:
• CLK_USART
• a division of CLK_USART, the divider being product dependent, but generally set to 8
• the external clock, available on the CLK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Gener-
ator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal
provided on CLK must be at least 4.5 times lower than CLK_USART.
Figure 25-2. Baud Rate Generator
25.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The
resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
16-bit Counter
CD
USCLKS
CD
CLK_USART
CLK_USART/DIV
Reserved
CLK
SYNC
SYNC
USCLKS= 3
FIDI
OVER
Sampling
Divider
BaudRate
Clock
Sampling
Clock
1
0
0
CLK
0
1
2
3
>1
1
1
0
0