Datasheet

56
32117D–AVR-01/12
AT32UC3C
It is also possible to reset the device by pulling the RESET_N pin low. This pin has an internal
pull-up, and does not need to be driven externally during normal operation. Table 7-4 on page
56 lists these and other reset sources supported by the Reset Controller.
Figure 7-3. Reset Controller Block Diagram
In addition to the listed reset types, the JTAG & aWire can keep parts of the device statically
reset. See JTAG and aWire documentation for details.
Table 7-4. Reset Description
Depending on the reset source, when a reset occurs, some parts of the device are not always
reset. Only the Power-on Reset (POR) will force a whole device reset. Refer to the table in the
Module Configuration section at the end of this chapter for further details. The latest reset cause
can be read in the RCAUSE register, and can be read during the applications boot sequence in
order to determine proper action.
Reset Source Description
Power-on Reset
Supply voltage below the Power-on Reset detector threshold
voltage V
POT
External Reset RESET_N pin asserted
Brown-out Reset
VDDCORE supply voltage below the Brown-out detector
threshold voltage
CPU Error
Caused by an illegal CPU access to external memory while
in Supervisor mode
Watchdog Timer See Watchdog Timer documentation
OCD See On-Chip Debug documentation
JTAG
Reset
Controller
RESET_N
Power-on Reset
Detector(s)
OCD
Watchdog Reset
RCAUSE
CPU, HSB, PBx
OCD, AST, WDT,
Clock Generator
Brown-out
Detector
AWIRE