Datasheet

32117D–AVR-01/12

AT32UC3C

Notes: 1. The sleep mode index is used as argument for the sleep instruction.

2. Only PB modules operational, as HSB module clocks are stopped.

3. WDT only available if clocked from pre-enabled OSC32K.

7.6.3.4 Precautions when entering sleep mode

Modules communicating with external circuits should normally be disabled before entering a

sleep mode that will stop the module operation. This will prevent erratic behavior caused by

entering or exiting sleep modes. Please refer to the relevant module documentation for recom-

mended actions.

Communication between the synchronous clock domains is disturbed when entering and exiting

sleep modes. Bus transactions over clock domains affected by the sleep mode are therefore not

recommended. The system may hang if the bus clocks are stopped during a bus transaction.

The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-

plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is

necessary.

When entering a sleep mode (except Idle mode), all HSB masters must be stopped before

entering the sleep mode. In order to let potential PBx write operations complete, the user should

let the CPU perform a PBx register read operation before issuing the sleep instruction. This will

stall the CPU until pending PBx operations have completed.

7.6.4 Divided PB Clocks

The clock generator in the Power Manager provides divided PBx clocks for use by peripherals

that require a prescaled PBx clock. This is described in the documentation for the relevant mod-

ules. The divided clocks are directly maskable, and are stopped in sleep modes where the PBx

clocks are stopped.

7.6.5 Reset Controller

The Reset Controller collects the various reset sources in the system and generates hard and

soft resets for the digital logic.

The device contains a Power-on Reset (POR) detector, which keeps the system reset until

power is stable. This eliminates the need for external reset circuitry to guarantee stable opera-

tion when powering up the device.

Table 7-3. Wake-up Sources

Index

(1)

Sleep Mode Wake-up Sources

0 Idle Synchronous, Asynchronous

1 Frozen Synchronous

(2)

, Asynchronous

2 Standby Asynchronous

3 Stop Asynchronous

4 DeepStop Asynchronous

5 Static Asynchronous

(3)