Datasheet

518
32117D–AVR-01/12
AT32UC3C
24.7.8 Interrupt Status Register
Name: ISR
Access Type: Read/Write
Offset: 0x24
Reset Value: 0x00000000
• PTZ: Pause Time Zero
This bit is set when the pause time register (PTR) decrements to zero.
This bit is cleared after read.
0: PTR > 0.
1: PTR = 0.
• PFR: Pause Frame Received
This bit is cleared after read.
0: No valid pause frame received.
1: Valid pause frame received.
• HRESP: Hresp Not OK
This bit is set when the DMA interface detects a bus error.
This bit is cleared after read.
0: HRESP is OK.
1: HRESP is not OK.
• ROVR: Receive Overrun
This bit is set when the receive overrun status bit is set (RSR.OVR).
This bit is cleared after read.
0: RSR.OVR is not set.
1: RSR.OVR has been set.
• TCOMP: Transmit Complete
This bit is set when a frame has been transmitted.
This bit is cleared after read.
0: Transmit is not completed.
1: Transmit is completed.
• TXERR: Transmit Error
This bit is set when transmit buffers exhausted in mid-frame.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - PTZ PFR HRESP ROVR - -
76543210
TCOMP TXERR RLE TUND TXUBR RXUBR RCOMP MFD