Datasheet

517
32117D–AVR-01/12
AT32UC3C
24.7.7 Receive Status Register
Name: RSR
Access Type: Read/Write
Offset: 0x20
Reset Value: 0x00000000
This register, when read, returns details of the status of a receive. Once read, individual bits may be cleared by writing a
one to them. It is not possible to write a bit to one by writing to the register.
• OVR: Receive Overrun
This bit is set when the DMA interface is unable to store the receive frame to memory, either because the bus was not granted in
time or because a bus error was returned. The buffer is recovered if this happens.
Write a one to clear this bit.
0: No receive overrun detected.
1: Receive overrun detected.
• REC: Frame Received
This bit is set when one or more frames have been received and placed in memory.
Write a one to clear this bit.
0: No frame received.
1: Frame received.
• BNA: Buffer Not Available
The DMA reads the pointer each time a new frame starts, until a valid pointer is found. This bit is set at each attempt that fails
even if it has not had a successful pointer read since it has been cleared.
Write a one to clear this bit.
0: Buffer is available.
1: Buffer is not available because an attempt was made to get a new buffer and the pointer indicated that it was owned by the
processor.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
- - - - - OVR REC BNA