Datasheet

513
32117D–AVR-01/12
AT32UC3C
24.7.4 Transmit Status Register
Name: TSR
Access Type: Read/Write
Offset: 0x14
Reset Value: 0x00000000
This register, when read, returns details of the status of a transmit. Once read, individual bits may be cleared by writing a
one to them. It is not possible to write a bit to one by writing to the register.
UND: Transmit Underrun
This bit is set when transmit DMA was not able to read data from memory, either because the bus was not granted in time or
because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC.
Write a one to clear this bit.
0: No transmit underrun.
1: Transmit underrun.
COMP: Transmit Complete
This bit is set when a frame has been transmitted.
Write a one to clear this bit.
0: Transmit is not completed.
1: Transmit is completed.
BEX: Buffers Exhausted Mid Frame
This bit is set if the buffers run out during transmission of a frame. Then transmission stops, FCS shall be bad and TX_ER is
asserted.
Write a one to clear to this bit.
0: Buffer is not exhausted.
1: Buffer is exhausted.
TGO: Transmit Go
0: Transmit is inactive.
1: Transmit is active.
RLE: Retry Limit Exceeded
This bit is set when retry limit has exceeded.
Write a one to clear this bit.
0: Retry limit is not exceeded.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- UND COMP BEX TGO RLE COL UBR