Datasheet

511
32117D–AVR-01/12
AT32UC3C
• RTY: Retry Test
0: Normal operation.
1: The back off between collisions is always one slot time. It helps testing the too many retries condition. Also used in the pause
frame tests to reduce the pause counters decrement time from 512 bit times, to every RX_CLK cycle.
• CLK: PB Clock Divider
Determines by what number system clock is divided to generate Divided PB Clock (DPC). For conformance with 802.3, DPC
must not exceed 2.5MHz (DPC is only active during MDIO read and write operations).
• EAE: External Address Match Enable
0: External address match is disabled.
1: External address match is enabled. Eam pin can be used to copy frames to memory.
• FS: Frame Size
0: Reject any frames above 1518 bytes.
1: Accept frames up to 1536 bytes.
• UNI: Unicast Hash Enable
0: Unicast hash is disabled.
1: Unicast hash is enabled. Unicast frames are received when the 6-bit hash function of the destination address points to a bit
that is set in the hash register.
• MTI: Multicast Hash Enable
0: Multicast hash is disabled.
1: Multicast hash is enabled. Multicast frames are received when the 6-bit hash function of the destination address points to a bit
that is set in the hash register.
• NBC: No Broadcast
0: Frames addressed to the broadcast address of all ones are received.
1: Frames addressed to the broadcast address of all ones are not received.
• JFRAME: Jumbo Frames
0: Jumbo frames are disabled.
1: Enable jumbo frames of up to 10240 bytes to be accepted.
• CAF: Copy All Frames
0: Copy all frames is disabled.
1: All valid frames are received.
• BR: Bitrate
0: Data is transmitted least significant nibble first.
1: Data is serialized and transmitted least significant bit first (10Mbps). Must be written before receive and transmit enable in the
network control register. Serial interface is configured with transmit and receive data being driven out on TXD[0] and received on
RXD[0] serially. Also the CRS and RX_DV are logically ORed together so either may be used as the data valid signal.
• FD: Full Duplex
0: Full duplex mode is disabled.
1: Full duplex mode is enabled. Transmit sub-module ignores the state of collision and carrier sense and allows receive while
transmitting. Also controls the half duplex pin.
• SPD: Speed
0: 10 Mbit/s speed.
1: 100 Mbit/s speed. Bit value is reflected on the SPEED pin.
CLK DPC
00 PB clock divided by 8 (PB clock up to 20 MHz)
01 PB clock divided by 16 (PB clock up to 40 MHz)
10 PB clock divided by 32 (PB clock up to 80 MHz)
11 PB clock divided by 64 (PB clock up to 160 MHz)