Datasheet

507
32117D–AVR-01/12
AT32UC3C
Statistics registers (PFR to TPF) should be read frequently enough to prevent loss of data. The
receive statistics registers are only incremented when the receive enable bit is set in the network
control register (NCR.RE). Write access to statistics registers is allowed if NCR.WESTAT is set.
Statistic registers are cleared on a read and stick at all ones when they count to their maximum
value.
0x94 Hash Register Top HRT Read/Write 0x00000000
0x98 Specific Address 1 Bottom Register SA1B Read/Write 0x00000000
0x9C Specific Address 1 Top Register SA1T Read/Write 0x00000000
0xA0 Specific Address 2 Bottom Register SA2B Read/Write 0x00000000
0xA4 Specific Address 2 Top Register SA2T Read/Write 0x00000000
0xA8 Specific Address 3 Bottom Register SA3B Read/Write 0x00000000
0xAC Specific Address 3 Top Register SA3T Read/Write 0x00000000
0xB0 Specific Address 4 Bottom Register SA4B Read/Write 0x00000000
0xB4 Specific Address 4 Top Register SA4T Read/Write 0x00000000
0xB8 Type ID Checking Register TID Read/Write 0x00000000
0xBC Transmit Pause Quantum Register TPQ Read/Write 0x0000FFFF
0xC0 User Input/output Register USRIO Read/Write 0x00000000
0xC4 Wake on LAN Register WOL Read/Write 0x00000000
0xFC Version Register VERSION Read-only -
(1)
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 24-6. MACB Register Memory Map (Continued)
Offset Register Register Name Access Reset