Datasheet

504
32117D–AVR-01/12
AT32UC3C
24.6.3 Transmit Buffer List
Transmit data is read from the system memory These buffers are listed in another data structure
that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of
descriptor entries (as defined in Table 24-2 on page 494) that points to this data structure.
To create this list of buffers:
1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted
in system memory. Up to 128 buffers per frame are allowed.
2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory
and create N entries in this list. Mark all entries in this list as owned by MACB, i.e. bit 31
of word 1 set to 0.
3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap
bit (bit 30 in word 1 set to 1).
4. Write address of transmit buffer descriptor entry to MACB register transmit buffer queue
pointer.
5. The transmit circuits can then be enabled by writing to the network control register.
24.6.4 Address Matching
The MACB register-pair hash address and the four specific address register-pairs must be writ-
ten with the required values. Each register-pair comprises a bottom register and top register,
with the bottom register being written first. The address matching is disabled for a particular reg-
ister-pair after the bottom-register has been written and re-enabled when the top register is
written. See Section “24.5.8” on page 497. for details of address matching. Each register-pair
may be written at any time, regardless of whether the receive circuits are enabled or disabled.
24.6.5 Interrupts
There are 14 interrupt conditions that are detected within the MACB. These are ORed to make a
single interrupt. This interrupt is handled by the interrupt controller. On receipt of the interrupt
signal, the CPU enters the interrupt handler. To ascertain which interrupt has been generated,
read the interrupt status register. Note that this register clears itself when read. At reset, all inter-
rupts are disabled. To enable an interrupt, write to interrupt enable register with the pertinent
interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent
interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask
register: if the bit is set to 1, the interrupt is disabled.
24.6.6 Transmitting Frames
To set up a frame for transmission:
1. Enable transmit in the network control register.
2. Allocate an area of system memory for transmit data. This does not have to be contigu-
ous, varying byte lengths can be used as long as they conclude on byte borders.
3. Set-up the transmit buffer list.
4. Set the network control register to enable transmission and enable interrupts.
5. Write data for transmission into these buffers.
6. Write the address to transmit buffer descriptor queue pointer.
7. Write control and length to word one of the transmit buffer descriptor entry.
8. Write to the transmit start bit in the network control register.