Datasheet

502
32117D–AVR-01/12
AT32UC3C
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in
the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in
Table 24-5.
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It
uses 2 bits for transmission (TXD[1:0]) and two bits for reception (RXD[1:0]). There are Transmit
Enable (TX_EN), a Receive Error (RX_ER), a Carrier Sense (CRS), and a 50 MHz Reference
Clock (TX_CLK) for 100Mb/s data rate.
24.5.17.1 RMII Transmit and Receive Operation
The same signals are used internally for both the RMII and the MII operations. The RMII maps
these signals in a more pin-efficient manner. The transmit and receive bits are converted from a
4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense
and data valid signals are combined into the RX_DV signal. This signal contains information on
carrier sense, FIFO status, and validity of the data. Transmit error bit (TX_ER) and collision
detect (COL) are not used in RMII mode.
Table 24-5. Pin Configuration
Pin Name MII RMII
TX_CLK Transmit Clock Reference Clock
CRS Carrier Sense
COL Collision Detect
RX_DV Data Valid Carrier Sense/Data Valid
RXD[3:0] RXS[3:0] 4-bit Receive Data RXD[1:0] 2-bit Receive Data
RX_ER Receive Error Receive Error
RX_CLK Receive Clock
TX_EN Transmit Enable Transmit Enable
TXD[3:0] TXD[3:0] 4-bit Transmit Data TXD[1:0] 2-bit Transmit Data
TX_ER Transmit Error