Datasheet

486
32117D–AVR-01/12
AT32UC3C
23.8 Module Configuration
The specific configuration for each GPIO instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager
chapter for details.
The reset values for all GPIO registers are zero, with the following exceptions:
Table 23-3. Module Configuration
Feature GPIO
Number of GPIO ports 4
Number of peripheral functions 4
Table 23-4. Implemented Pin Functions
Pin Function Implemented Notes
Pull-up Yes Controlled by PUER or peripheral
Pull-down Yes Controlled by PDER
Drive strength Yes Writing to ODCR0 control the drive strength of the pads
Writing to ODCR1 has no effect
Slew rate No OSRRn registers are not implemented
Open Drain No ODMERn registers are not implemented
Bus keeper No Setting {PUER, PDER} to 0x3 in a pin does not enable
the bus keeper on this pin
Table 23-5. Module Clock Name
Module name Clock Name Description
GPIO CLK_GPIO Peripheral Bus clock from the PBA clock domain
Table 23-6. Register Reset Values
Port Register Reset Value
0 GPER 0x3FF9FFFF
0 PMR0 0x00000001
0 PMR1 - PMR2 0x00000000
0 ODER - OVR 0x00000000
0 PUER 0x00000001
0 PDER 0x00000000
0 IER - IMR0 - IMR1 - IFR 0x00000000
0 GFER 0x3FF9FFFF
0 ODCR0 0x00000000
0 LOCK 0x00000000
0 PARAMETER 0x3FF9FFFF