Datasheet

441
32117D–AVR-01/12
AT32UC3C
22.6.3 Channel Enable Register High
Name: CERH
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
• CERH[n]: Channel Enable Register High
0: Channel (n+32) is not enabled.
1: Channel (n+32) is enabled.
31 30 29 28 27 26 25 24
- CERH[30:24]
23 22 21 20 19 18 17 16
CERH[23:16]
15 14 13 12 11 10 9 8
CERH[15:8]
76543210
CERH[7:0]