Datasheet

431
32117D–AVR-01/12
AT32UC3C
21.8 Module Configuration
The specific configuration for each MDMA instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager
chapter for details.
Table 21-6. Module Configuration
Feature MDMA
Channels 1
Maximum burst size Single Transfer
Table 21-7. Module Clock Name
Module name Clock name Description
MDMA
CLK_MDMA_HSB HSB clock
CLK_MDMA_PB Peripheral Bus clock from the PBC clock domain
Table 21-8. Register Reset Values
Register Reset Value
VR 0x00000101
PR 0x00000001