Datasheet

421
32117D–AVR-01/12
AT32UC3C
21.7.5 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x000000000
• BERRx: Channel Bus Error
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when the channel has encountered a bus error and has an interrupt request pending. Upon receiving a bus error,
the affected channel is automatically disabled.
• CHxC: Channel Complete
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when the channel has completed a transfer and has an interrupt request pending.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
----BERR3BERR2BERR1BERR0
76543210
----CH3CCH2CCH1CCH0C