Datasheet

412
32117D–AVR-01/12
AT32UC3C
21.3.4 Debug Operation
When an external debugger forces the CPU into debug mode, the MDMA continues normal
operation. If the MDMA is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during debugging.
21.4 Functional Description
21.4.1 Bus Interfaces
The MDMA has three bus interfaces, two High-Speed Bus interfaces for data and descriptor
transfer, and one Peripheral Bus interface for writing control information to and reading status
information from the controller.
21.4.2 Transferring Data
Once a channel (x) is selected by the arbiter, data of the size given by the SIZE field in the
Channel Control Register (CCRx.SIZE) will be transferred from consecutive addresses starting
as specified in the Read Address Register (RARx) to consecutive addresses starting as speci-
fied in the Write Address Register (WARx). The number of data to be transferred is given by the
Transfer Count field (CCRx.TCNT). The MDMA will try to transfer data in bursts with burst size
given by CCRx.BURST. The MDMA is free to use bursts of smaller size if this is required by the
bus semantics or if TCNT is not perfectly divisible by BURST.
During transfers, TCNT is continuously decremented until it reaches zero, indicating that the
transfer has completed. RARx and WARx are not changed by hardware during transfers.
Data read from the bus is put into a FIFO before being written to the bus. The FIFO has word-
sized entries, so any halfwords or bytes transferred from the bus will be zero-extended before
being put in the FIFO. Words are not extended in any way. The Byte Swap (BSWP) field in
CCRx determines if any modifications are to be performed on the read data from the zero-exten-
sion unit. This allows data reformatting such as endianness-conversion.
Figure 21-1. Byte Swapping the FIFO Inputs
21.4.3 Arbitration
Arbitration between the channels is performed at the end of each burst. If no other channels
have pending transfers, the current channel continues uninterrupted.
In Fixed Priority Mode, if a channel of higher priority is enabled when another channel is trans-
ferring data, the channel of higher priority will preempt the other channel. When the preempting
channel has completed, the arbiter will grant control to the original channel so it can complete its
transfer.
Zero-
extend
Byte
swap
Read dataWrite data
FIFO