Datasheet

409
32117D–AVR-01/12
AT32UC3C
20.8 Module Configuration
The specific configuration for the PDCA instance is listed in the following tables.
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 20-6. PDCA Configuration
Features PDCA
Number of channels 16
Number of performance monitors 1
Table 20-7. Module Clock Name
Module name Clock name Description
PDCA
CLK_PDCA_HSB HSB clock
CLK_PDCA_PB Peripheral Bus clock from the PBC clock domain
Table 20-8. Register Reset Values
Register Reset Value
PSRn n
VERSION 0x123
Table 20-9. Peripheral Identity Values
PID Direction Peripheral Instance Peripheral Register
0 RX ADCIFA LCV0
1 RX ADCIFA LCV1
2 RX USART0 RHR
3 RX USART1 RHR
4 RX USART2 RHR
5 RX USART3 RHR
6 RX TWIM0 RHR
7 RX TWIM1 RHR
8 RX TWIS0 RHR
9 RX TWIS1 RHR
10 RX SPI0 RDR
11 RX SPI1 RDR
12 RX AW RHR
13 TX USART0 THR
14 TX USART1 THR
15 TX USART2 THR
16 TX USART3 THR