Datasheet

358
32117D–AVR-01/12
AT32UC3C
and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR
register, and transmitted to the low power SDRAM device during initialization.
After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and
self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command
to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automati-
cally. The PASR/DS/TCSR parameters values are therefore updated before entry into self
refresh mode.
The SDRAM device must remain in self refresh mode for a minimum period of t
RAS
and may
remain in self refresh mode for an indefinite period. This is described in Figure 19-8 on page
358.
Figure 19-8. Self Refresh Mode Behavior
19.7.6.2 Low power mode
This mode is selected by writing the value two to the LPR.LPCB field. Power consumption is
greater than in self refresh mode. All the input and output buffers of the SDRAM device are
deactivated except SDCKE, which remains low. In contrast to self refresh mode, the SDRAM
device cannot remain in low power mode longer than the refresh period (64ms for a whole
device refresh operation). As no auto refresh operations are performed by the SDRAM itself, the
SDRAMC carries out the refresh operation. The exit procedure is faster than in self refresh
mode.
This is described in Figure 19-9 on page 359.
SDRAMC_A[12:0]
SDCK
SDCKE
SDCS
RAS
CAS
Access Request
To the SDRAM Controller
Self Refresh Mode
Row
T
XSR
= 3
SDWE