Datasheet

304
32117D–AVR-01/12
AT32UC3C
17.6 Functional Description
The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control busses and is composed of the following elements:
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different memory controllers
17.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 16(8)-bit data lines, the address
lines of up to 24 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the
other external memory controller accesses.
17.6.2 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
17.6.3 SDRAM Controller
Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic.
For information on the SDRAM Controller, refer to the SDRAM Section.
17.7 Application Example
17.7.1 Hardware Interface
Table 17-4. EBI Pins and External Static Devices Connections
Pins name
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
Controller SMC
DATA[7:0] D[7:0] D[7:0] D[7:0]
DATA[15:0] – D[15:8] D[15:8]
ADDR[0] A[0] – NBS0
(2)
ADDR[1] A[1] A[0] A[0]
ADDR[23:2] A[23:2] A[22:1] A[22:1]
NCS[0] - NCS[3] CS CS CS