Datasheet

301
32117D–AVR-01/12
AT32UC3C
17.3 Block Diagram
Figure 17-1. EBI Block Diagram
17.4 I/O Lines Description
HSB
HMATRIX
EBI
SDRAM
Controller
Static
Memory
Controller
MUX
Logic
Peripheral Bus
I/O
Controller
DATA[15:0]
NWE1
NWE0
NRD
NCS[3:0]
ADDR[23:0]
CAS
RAS
SDA10
SDWE
SDCK
SDCKE
NWAIT
INTC
SDRAMC_irq
Chip Select
Assignor
Address
Decoders
SFR
registers
HSB-PB
Bridge