Datasheet

298
32117D–AVR-01/12
AT32UC3C
16.6 Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, MCFG0 is associated
with the CPU Data master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is
associated with the Internal SRAM Slave Interface.
Table 16-3. High Speed Bus masters
Master 0 CPU Data
Master 1 CPU Instruction
Master 2 CPU SAB
Master 3 SAU
Master 4 PDCA
Master 5 MDMA Read
Master 6 MDMA write
Master 7 USBC
Master 8 CANIF
Master 9 MACB
Table 16-4. High Speed Bus slaves
Slave 0 Internal Flash
Slave 1 HSB-PB Bridge A
Slave 2 HSB-PB Bridge B
Slave 3 HSB-PB Bridge C
Slave 4 Internal SRAM
Slave 5 HSB RAM
Slave 6 EBI
Slave 7 SAU