Datasheet

266
32117D–AVR-01/12
AT32UC3C
15.8 User interface
Note: 1. The value of the Lock bits is dependent of their programmed state. All other bits in FSR are 0. All bits in FGPFR are depen-
dent on the programmed state of the fuses they map to. Any bits in these registers not mapped to a fuse read 0.
2. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
Table 15-5. FLASHC Register Memory Map
Offset Register Register Name Access Reset
0x0 Flash Control Register FCR Read/Write 0x00000000
0x4 Flash Command Register FCMD Read/Write 0x00000000
0x8 Flash Status Register FSR Read/Write 0
(1)
0xc Flash Parameter Register PR Read-only 0
(2)
0x10 Flash Version Register VR Read-only 0
(2)
0x14 Flash General Purpose Fuse Register Hi FGPFRHI Read-only NA
(1)
0x18 Flash General Purpose Fuse Register Lo FGPFRLO Read-only NA
(1)