Datasheet

256
32117D–AVR-01/12
AT32UC3C
The FLASHC can also operate in systems where the HSB bus clock period is faster than the
access speed of the flash memory. Wait state support and a read granularity of 64 bits ensure
efficiency in such systems.
Performance for systems with high clock frequency is increased since the flash internally is con-
figured as two separate banks of 32 bits. Each bank has its own read port. In 0ws mode, only
one of the two flash read ports is accessed. The other flash read port is idle. In 1ws mode, both
flash read ports are active. One read port reading the addressed word, and the other reading the
next sequential word.
The programmer can select the wait states required by writing to the FWS field in the Flash Con-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash memory.
In 0ws mode, no wait states are encountered on any flash read operations. In 1 ws mode, one
stall cycle is encountered on the first access in a single or burst transfer.
If the clock frequency allows, the user should use 0ws mode, because this gives the lowest
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the
power, but also give twice the performance.
The Flash Controller address space is displayed in Figure 15-1. The memory space between
address pw and the User page is reserved, and reading addresses in this space returns an
undefined result. The User page is permanently mapped to an offset of 0x0080 0000 from the
start address of the flash memory. The Factory page is permanently mapped to an offset of
0x0080 0200 from the start address of the flash memory.
Table 15-1. User page Addresses
Memory type Start address, byte sized Size
Main array 0 pw bytes
User 0x0080 0000 w bytes
Factory Page 0x0080 0200 w bytes